AMD EPYC 9535

The AMD EPYC 9535 is a 64-core server processor from the EPYC 9005 series, built on the Zen 5 architecture (codename Turin) using a 4 nm process at TSMC. It operates at a base clock of 2.40 GHz and a boost clock of 4.30 GHz, with a TDP of 300 W. The chip is designed for the AMD Socket SP5 platform and supports twelve-channel DDR5 memory with a bandwidth of 576.0 GB/s, along with ECC memory. It provides 128 PCIe Gen 5 lanes (CPU only) and is targeted at the server and workstation market segment. The processor was released on 2024-10-09 and carries a launch MSRP of $8992.

Benchmark Performance

The fact pack does not include any benchmark scores or nearest-rival data. The only performance-related field is a percentile of 50 against all CPUs, which suggests a median position in the database, but without actual scores this cannot be interpreted as a performance level. The average benchmark score is 0, further indicating that no measured results are available. Consequently, quantitative deltas cannot be reported. Instead, the hardware specifications provide a basis for expectation. With 64 Zen 5 cores and simultaneous multithreading (128 threads), the processor should deliver strong throughput in heavily threaded workloads. The 256 MB shared L3 cache and 576.0 GB/s memory bandwidth are indicative of high data-processing capability. The boost clock of 4.30 GHz is notably high for a 64-core server part, suggesting that single-threaded tasks can also achieve substantial performance when only a few cores are active. The 300 W TDP reflects the power envelope required to sustain these clock speeds across the entire chip.

How It Compares

The nearestRivals list in the fact pack is empty, so direct comparisons to other processors are not available. The processor's own specifications place it in the high-core-count segment of the EPYC 9005 series. With 64 cores and 128 threads, it sits above typical 32-core parts, but without rival data we cannot quantify the difference. The percentile of 50 indicates it is at the median of the database's CPU population, which may reflect the lack of benchmark entries rather than actual performance. The absence of rival scores means that any positional analysis must rely solely on the architectural characteristics: the 4 nm process, the 66,520 million transistors across 8 dies (each 70.6 mm²), and the 256 MB L3 cache all point to a design optimized for high-core-count, memory-intensive workloads.

Who Should Consider It

Given its 64 cores and 128 threads, this processor is suited for server and workstation workloads that benefit from high parallelism, such as virtualization, database processing, scientific simulations, and large-scale data analysis. The 4.30 GHz boost clock also supports moderate single-thread performance, making it capable of handling interactive or latency-sensitive tasks. The 256 MB L3 cache and 576.0 GB/s memory bandwidth are advantageous for workloads with large working sets, as they reduce the frequency of slower memory accesses. The 128 PCIe Gen 5 lanes (CPU only) allow for extensive I/O connectivity, including multiple GPUs or NVMe storage arrays. The 300 W TDP indicates a high power draw, so it is intended for systems with robust cooling and power delivery. Organizations that deploy many virtual machines, run large in-memory databases, or perform complex simulations will find the core count and memory throughput compelling. Conversely, workloads that are primarily single-threaded or have low memory bandwidth requirements may not fully utilize this processor's capabilities.

FAQ

Q: What is the core and thread count of the AMD EPYC 9535?

A: It has 64 cores and 128 threads.

Q: What is the boost clock speed?

A: The boost clock is 4.30 GHz.

Q: What memory configuration does it support?

A: It supports DDR5 memory in a twelve-channel configuration with a bandwidth of 576.0 GB/s, and ECC memory is supported.

Q: What socket does it use?

A: It uses AMD Socket SP5.

Q: What is the launch MSRP?

A: The launch MSRP is $8992.

Q: What is the process node?

A: It is built on a 4 nm process at TSMC.

Platform and Compatibility

The EPYC 9535 is designed for the AMD Socket SP5 platform. It supports DDR5 memory with a twelve-channel bus, providing a total bandwidth of 576.0 GB/s. ECC memory is supported, which is critical for data integrity in server environments. The processor provides 128 PCIe Gen 5 lanes (CPU only), which can be used for high-speed peripherals such as GPUs, storage controllers, and network adapters. The processor is part of the EPYC 9005 series, and its production status is active. The launch date is 2024-10-09. The die is composed of 8 chiplets, each 70.6 mm², with a total of 66,520 million transistors. The architecture is Zen 5, with a 4 nm process from TSMC. This platform is intended for dual-socket or single-socket server configurations, though the fact pack does not specify multi-socket support. The 300 W TDP requires appropriate cooling solutions, typically large heatsinks or liquid cooling, and a power delivery system capable of sustaining that draw.

Single-Thread vs Multi-Thread Behavior

The EPYC 9535 has a base clock of 2.40 GHz and a boost clock of 4.30 GHz. The boost clock is relatively high for a 64-core server processor, indicating that single-threaded tasks can achieve substantial performance when only a few cores are active. However, the primary strength is multi-threading: with 128 threads, the processor can handle highly parallel workloads. The large 256 MB L3 cache helps reduce memory latency, which benefits both single- and multi-threaded applications by keeping frequently accessed data close to the cores. The twelve-channel memory interface with 576.0 GB/s bandwidth ensures that data can feed all cores simultaneously, preventing memory bandwidth from becoming a bottleneck in multi-threaded scenarios. The TDP of 300 W reflects the power needed to sustain high clock speeds across all cores. In practice, workloads that are embarrassingly parallel, such as rendering, scientific computing, or large-scale data processing, will see near-linear scaling with core count, while single-threaded tasks will rely on the boost clock and cache efficiency. The balance of high core count and competitive boost clock makes this processor versatile, though its design clearly prioritizes throughput over raw single-core speed.