CPU Comparison

A

AMD

AMD

AMD EPYC 7352

CORE STATE Rome

CORE SPECS 24 Cores / 48 Threads

CLOCK SPEED 2.3 Base / 3.2 GHz Turbo

CACHE 32 MB (per die)

MAX TDP 155W

ARCHITECTURE Zen 2

nm

PROCESS 7 nm

LAUNCH DATE 2019

VS

A

AMD

AMD

EPYC 9655

CORE STATE Turin

CORE SPECS 96 Cores / 192 Threads

CLOCK SPEED 2.6 Base / 4.5 GHz Turbo

CACHE 384 MB (shared)

MAX TDP 400W

ARCHITECTURE Zen 5

nm

PROCESS 4 nm

LAUNCH DATE 2024

PERFORMANCE BENCHMARKS

cinebench_cinebench_r15_multicore

3,458

13,373

cinebench_cinebench_r15_singlecore

488

1,887

cinebench_cinebench_r20_multicore

14,411

55,722

cinebench_cinebench_r20_singlecore

2,034

7,866

cinebench_cinebench_r23_multicore

34,314

132,672

cinebench_cinebench_r23_singlecore

4,844

18,730

passmark_data_compression

660,712

3,271,019

passmark_data_encryption

44,426

210,541

passmark_extended_instructions

40,203

203,302

passmark_find_prime_numbers

301

1,599

passmark_floating_point_math

87,969

662,949

passmark_integer_math

148,605

1,139,221

passmark_multithread

40,370

156,085

passmark_physics

2,688

25,958

passmark_random_string_sorting

69,231

440,608

passmark_single_thread

1,979

3,845

passmark_singlethread

1,979

3,845

DETAILED SPECIFICATIONS

SPECIFICATION

EPYC 7352

EPYC 9655

Core Specs

Cores

24

96 +300.0%

Threads

48

192 +300.0%

Base Clock (GHz)

2.3

2.6 +13.0%

Boost Clock (GHz)

3.2

4.5 +40.6%

Frequency (GHz)

2.3

2.6 +13.0%

Turbo Clock (GHz)

3.2

4.5 +40.6%

Multiplier

23

26 +13.0%

SMP CPUs

2

2 0.0%

Cache

L1 Cache

96 KB (per core)

80 KB (per core)

L2 Cache

512 KB (per core)

1 MB (per core)

L3 Cache

32 MB (per die)

384 MB (shared)

Total L3

128 MB

—

Power

TDP (W)

155

400 +158.1%

Configurable TDP

180 W

320-400 W

Architecture

Architecture

Zen 2

Zen 5

Codename

Rome

Turin

Generation

EPYC (Zen 2 (Rome))

EPYC (Zen 5 (Turin))

Process Size

7 nm

4 nm

Transistors

15,200 million

99,780 million

Die Size

4x 74 mm²

12x 70.6 mm²

Foundry

TSMC

TSMC

Memory

Memory Support

DDR4

DDR5

Memory Bus

Eight-channel

Twelve-channel

Memory Bandwidth

204.8 GB/s

576.0 GB/s

ECC Memory

Yes

Yes

Platform

Socket

AMD Socket SP3

AMD Socket SP5

PCIe

Gen 4, 128 Lanes(CPU only)

Gen 5, 128 Lanes(CPU only)

AMD Multi-Die

CCDs

4

—

Cores per CCD

6

—

IO Process Size

14 nm

6 nm

Interconnect

CXL

—

Gen 2.0

Other

Market

Server/Workstation

Server/Workstation

Production Status

Active

Active

Launch Price

$1350

$11852

Part Number

100-000000077

100-000000674

Package

FCLGA-4094

FC-LGA6096

View EPYC 7352 Details View EPYC 9655 Details