CPU Comparison

AMD
AMD

AMD EPYC 7352

CORE STATE Rome
CORE SPECS 24 Cores / 48 Threads
CLOCK SPEED 2.3 Base / 3.2 GHz Turbo
CACHE 32 MB (per die)
MAX TDP 155W
ARCHITECTURE Zen 2
nm
PROCESS 7 nm
LAUNCH DATE 2019
VS
AMD
AMD

EPYC 9565

CORE STATE Turin
CORE SPECS 72 Cores / 144 Threads
CLOCK SPEED 3.15 Base / 4.3 GHz Turbo
CACHE 384 MB (shared)
MAX TDP 400W
ARCHITECTURE Zen 5
nm
PROCESS 4 nm
LAUNCH DATE 2024

PERFORMANCE BENCHMARKS

cinebench_cinebench_r15_multicore
3,458
11,585
cinebench_cinebench_r15_singlecore
488
1,635
cinebench_cinebench_r20_multicore
14,411
48,273
cinebench_cinebench_r20_singlecore
2,034
6,814
cinebench_cinebench_r23_multicore
34,314
114,937
cinebench_cinebench_r23_singlecore
4,844
16,226
passmark_data_compression
660,712
2,579,631
passmark_data_encryption
44,426
141,936
passmark_extended_instructions
40,203
209,595
passmark_find_prime_numbers
301
2,422
passmark_floating_point_math
87,969
549,422
passmark_integer_math
148,605
717,948
passmark_multithread
40,370
135,221
passmark_physics
2,688
18,036
passmark_random_string_sorting
69,231
291,941
passmark_single_thread
1,979
3,696
passmark_singlethread
1,979
3,696

DETAILED SPECIFICATIONS

SPECIFICATION
EPYC 7352
EPYC 9565
Core Specs
Cores
24
72 +200.0%
Threads
48
144 +200.0%
Base Clock (GHz)
2.3
3.15 +37.0%
Boost Clock (GHz)
3.2
4.3 +34.4%
Frequency (GHz)
2.3
3.15 +37.0%
Turbo Clock (GHz)
3.2
4.3 +34.4%
Multiplier
23
31.5 +37.0%
SMP CPUs
2
2 0.0%
Cache
L1 Cache
96 KB (per core)
80 KB (per core)
L2 Cache
512 KB (per core)
1 MB (per core)
L3 Cache
32 MB (per die)
384 MB (shared)
Total L3
128 MB
Power
TDP (W)
155
400 +158.1%
Configurable TDP
180 W
320-400 W
Architecture
Architecture
Zen 2
Zen 5
Codename
Rome
Turin
Generation
EPYC (Zen 2 (Rome))
EPYC (Zen 5 (Turin))
Process Size
7 nm
4 nm
Transistors
15,200 million
99,780 million
Die Size
4x 74 mm²
12x 70.6 mm²
Foundry
TSMC
TSMC
Memory
Memory Support
DDR4
DDR5
Memory Bus
Eight-channel
Twelve-channel
Memory Bandwidth
204.8 GB/s
576.0 GB/s
ECC Memory
Yes
Yes
Platform
Socket
AMD Socket SP3
AMD Socket SP5
PCIe
Gen 4, 128 Lanes(CPU only)
Gen 5, 128 Lanes(CPU only)
AMD Multi-Die
CCDs
4
Cores per CCD
6
IO Process Size
14 nm
6 nm
Interconnect
CXL
Gen 2.0
Other
Market
Server/Workstation
Server/Workstation
Production Status
Active
Active
Launch Price
$1350
$10486
Part Number
100-000000077
100-000001447
Package
FCLGA-4094
FC-LGA6096
View EPYC 7352 Details View EPYC 9565 Details