CPU Comparison

AMD
AMD

AMD EPYC 7352

CORE STATE Rome
CORE SPECS 24 Cores / 48 Threads
CLOCK SPEED 2.3 Base / 3.2 GHz Turbo
CACHE 32 MB (per die)
MAX TDP 155W
ARCHITECTURE Zen 2
nm
PROCESS 7 nm
LAUNCH DATE 2019
VS
AMD
AMD

EPYC 9135

CORE STATE Turin
CORE SPECS 16 Cores / 32 Threads
CLOCK SPEED 3.65 Base / 4.3 GHz Turbo
CACHE 64 MB (shared)
MAX TDP 200W
ARCHITECTURE Zen 5
nm
PROCESS 4 nm
LAUNCH DATE 2024

PERFORMANCE BENCHMARKS

cinebench_cinebench_r15_multicore
3,458
4,952
cinebench_cinebench_r15_singlecore
488
699
cinebench_cinebench_r20_multicore
14,411
20,637
cinebench_cinebench_r20_singlecore
2,034
2,913
cinebench_cinebench_r23_multicore
34,314
49,136
cinebench_cinebench_r23_singlecore
4,844
6,936
passmark_data_compression
660,712
737,167
passmark_data_encryption
44,426
40,941
passmark_extended_instructions
40,203
54,795
passmark_find_prime_numbers
301
299
passmark_floating_point_math
87,969
125,125
passmark_integer_math
148,605
204,258
passmark_multithread
40,370
57,808
passmark_physics
2,688
6,096
passmark_random_string_sorting
69,231
92,226
passmark_single_thread
1,979
3,672
passmark_singlethread
1,979
3,672

DETAILED SPECIFICATIONS

SPECIFICATION
EPYC 7352
EPYC 9135
Core Specs
Cores
24
16 -33.3%
Threads
48
32 -33.3%
Base Clock (GHz)
2.3
3.65 +58.7%
Boost Clock (GHz)
3.2
4.3 +34.4%
Frequency (GHz)
2.3
3.65 +58.7%
Turbo Clock (GHz)
3.2
4.3 +34.4%
Multiplier
23
36.5 +58.7%
SMP CPUs
2
2 0.0%
Cache
L1 Cache
96 KB (per core)
80 KB (per core)
L2 Cache
512 KB (per core)
1 MB (per core)
L3 Cache
32 MB (per die)
64 MB (shared)
Total L3
128 MB
Power
TDP (W)
155
200 +29.0%
Configurable TDP
180 W
200-240 W
Architecture
Architecture
Zen 2
Zen 5
Codename
Rome
Turin
Generation
EPYC (Zen 2 (Rome))
EPYC (Zen 5 (Turin))
Process Size
7 nm
4 nm
Transistors
15,200 million
16,630 million
Die Size
4x 74 mm²
2x 70.6 mm²
Foundry
TSMC
TSMC
Memory
Memory Support
DDR4
DDR5
Memory Bus
Eight-channel
Twelve-channel
Memory Bandwidth
204.8 GB/s
576.0 GB/s
ECC Memory
Yes
Yes
Platform
Socket
AMD Socket SP3
AMD Socket SP5
PCIe
Gen 4, 128 Lanes(CPU only)
Gen 5, 128 Lanes(CPU only)
AMD Multi-Die
CCDs
4
Cores per CCD
6
IO Process Size
14 nm
6 nm
Interconnect
CXL
Gen 2.0
Other
Market
Server/Workstation
Server/Workstation
Production Status
Active
Active
Launch Price
$1350
$1214
Part Number
100-000000077
100-000001150
Package
FCLGA-4094
FC-LGA6096
View EPYC 7352 Details View EPYC 9135 Details