CPU Comparison
AMD
AMD Ryzen 5 7400
CORE STATE
Raphael
CORE SPECS
6 Cores / 12 Threads
CLOCK SPEED
3.3 Base / 4.3 GHz Turbo
CACHE
16 MB (shared)
MAX TDP
65W
ARCHITECTURE
Zen 4
PROCESS
5 nm
LAUNCH DATE
2025
VS
INTEL
Xeon 6980E+
CORE STATE
Clearwater Forest
CORE SPECS
264 Cores / 264 Threads
CLOCK SPEED
2.1 Base / 3.2 GHz Turbo
CACHE
528 MB (shared)
MAX TDP
400W
ARCHITECTURE
Clearwater Forest
PROCESS
3 nm
LAUNCH DATE
2026
PERFORMANCE BENCHMARKS
passmark_data_compression
passmark_data_encryption
passmark_extended_instructions
passmark_find_prime_numbers
passmark_floating_point_math
passmark_integer_math
passmark_multithread
passmark_physics
passmark_random_string_sorting
passmark_single_thread
passmark_singlethread
DETAILED SPECIFICATIONS
SPECIFICATION
5 7400
6980E+
Core Specs
Cores
6
264
+4300.0%
Threads
12
264
+2100.0%
Base Clock (GHz)
3.3
2.1
-36.4%
Boost Clock (GHz)
4.3
3.2
-25.6%
Frequency (GHz)
3.3
2.1
-36.4%
Turbo Clock (GHz)
4.3
3.2
-25.6%
Multiplier
33
21
-36.4%
SMP CPUs
1
2
+100.0%
Cache
L1 Cache
64 KB (per core)
96 KB (per core)
L2 Cache
1 MB (per core)
4 MB (per module)
L3 Cache
16 MB (shared)
528 MB (shared)
Power
TDP (W)
65
400
+515.4%
PPT
88 W
—
Architecture
Architecture
Zen 4
—
Codename
Raphael
Clearwater Forest
Generation
Ryzen 5
(Zen 4 (Raphael))
Xeon 6+
(Clearwater Forest-SP)
Process Size
5 nm
3 nm
Transistors
6,570 million
—
Die Size
71 mm²
—
Foundry
TSMC
Intel
Memory
Memory Support
DDR5
DDR5
Memory Bus
Dual-channel
Twelve-channel
Memory Bandwidth
83.2 GB/s
768.0 GB/s
ECC Memory
Yes
Yes
Platform
Socket
AMD Socket AM5
Intel Socket 7529
Chipsets
X670E, X670, B650E, B650, A620, X870E, X870, B850, B840
—
PCIe
Gen 5, 24 Lanes(CPU only)
Gen 5, 96 Lanes(CPU only)
AMD Multi-Die
IO Process Size
6 nm
10 nm
Interconnect
UPI Links
—
6x 24 GT/s
CXL
—
Gen 2.0, 64 Lanes (Shared with PCI-E)
Graphics
Integrated Graphics
Radeon Graphics
—
Other
Market
Desktop
Server/Workstation
Production Status
Active
Active
Part Number
100-000001900
unknown
Package
FC-LGA1718
FC-LGA18N
Tj Max
95°C
99°C
Bundled Cooler
Wraith Stealth
None