CPU Comparison

AMD
AMD

AMD EPYC 9455P

CORE STATE Turin
CORE SPECS 48 Cores / 96 Threads
CLOCK SPEED 3.15 Base / 4.4 GHz Turbo
CACHE 256 MB (shared)
MAX TDP 300W
ARCHITECTURE Zen 5
nm
PROCESS 4 nm
LAUNCH DATE 2024
VS
AMD
AMD

EPYC 9555P

CORE STATE Turin
CORE SPECS 64 Cores / 128 Threads
CLOCK SPEED 3.2 Base / 4.4 GHz Turbo
CACHE 256 MB (shared)
MAX TDP 360W
ARCHITECTURE Zen 5
nm
PROCESS 4 nm
LAUNCH DATE 2024

PERFORMANCE BENCHMARKS

cinebench_cinebench_r15_multicore
9,999
11,610
cinebench_cinebench_r15_singlecore
1,411
1,638
cinebench_cinebench_r20_multicore
41,666
48,378
cinebench_cinebench_r20_singlecore
5,882
6,829
cinebench_cinebench_r23_multicore
99,206
115,186
cinebench_cinebench_r23_singlecore
14,005
16,261
passmark_data_compression
1,932,632
2,630,921
passmark_data_encryption
115,202
155,805
passmark_extended_instructions
138,505
180,317
passmark_find_prime_numbers
1,089
1,156
passmark_floating_point_math
358,673
480,435
passmark_integer_math
606,087
821,218
passmark_multithread
116,713
135,513
passmark_physics
16,647
19,907
passmark_random_string_sorting
241,849
325,662
passmark_single_thread
3,750
3,726
passmark_singlethread
3,750
3,726

DETAILED SPECIFICATIONS

SPECIFICATION
EPYC 9455P
EPYC 9555P
Core Specs
Cores
48
64 +33.3%
Threads
96
128 +33.3%
Base Clock (GHz)
3.15
3.2 +1.6%
Boost Clock (GHz)
4.4
4.4 0.0%
Frequency (GHz)
3.15
3.2 +1.6%
Turbo Clock (GHz)
4.4
4.4 0.0%
Multiplier
31.5
32 +1.6%
SMP CPUs
1
1 0.0%
Cache
L1 Cache
80 KB (per core)
80 KB (per core)
L2 Cache
1 MB (per core)
1 MB (per core)
L3 Cache
256 MB (shared)
256 MB (shared)
Power
TDP (W)
300
360 +20.0%
Configurable TDP
240-300 W
320-400 W
Architecture
Architecture
Zen 5
Zen 5
Codename
Turin
Turin
Generation
EPYC (Zen 5 (Turin))
EPYC (Zen 5 (Turin))
Process Size
4 nm
4 nm
Transistors
66,520 million
66,520 million
Die Size
8x 70.6 mm²
8x 70.6 mm²
Foundry
TSMC
TSMC
Memory
Memory Support
DDR5
DDR5
Memory Bus
Twelve-channel
Twelve-channel
Memory Bandwidth
576.0 GB/s
576.0 GB/s
ECC Memory
Yes
Yes
Platform
Socket
AMD Socket SP5
AMD Socket SP5
PCIe
Gen 5, 128 Lanes(CPU only)
Gen 5, 128 Lanes(CPU only)
AMD Multi-Die
IO Process Size
6 nm
6 nm
Interconnect
CXL
Gen 2.0
Gen 2.0
Other
Market
Server/Workstation
Server/Workstation
Production Status
Active
Active
Launch Price
$4819
$7983
Part Number
100-000001563
100-000001523
Package
FC-LGA6096
FC-LGA6096
View EPYC 9455P Details View EPYC 9555P Details