CPU Comparison

A

AMD

AMD

AMD EPYC 8534P

CORE STATE Siena

CORE SPECS 64 Cores / 128 Threads

CLOCK SPEED 2.3 Base / 3.1 GHz Turbo

CACHE 128 MB (shared)

MAX TDP 200W

ARCHITECTURE Zen 4c

nm

PROCESS 5 nm

LAUNCH DATE 2023

VS

A

AMD

AMD

EPYC 9455P

CORE STATE Turin

CORE SPECS 48 Cores / 96 Threads

CLOCK SPEED 3.15 Base / 4.4 GHz Turbo

CACHE 256 MB (shared)

MAX TDP 300W

ARCHITECTURE Zen 5

nm

PROCESS 4 nm

LAUNCH DATE 2024

PERFORMANCE BENCHMARKS

cinebench_cinebench_r15_multicore

6,160

9,999

cinebench_cinebench_r15_singlecore

869

1,411

cinebench_cinebench_r20_multicore

25,668

41,666

cinebench_cinebench_r20_singlecore

3,623

5,882

cinebench_cinebench_r23_multicore

61,115

99,206

cinebench_cinebench_r23_singlecore

8,628

14,005

passmark_data_compression

1,791,742

1,932,632

passmark_data_encryption

121,728

115,202

passmark_extended_instructions

112,860

138,505

passmark_find_prime_numbers

278

1,089

passmark_floating_point_math

289,443

358,673

passmark_integer_math

514,526

606,087

passmark_multithread

71,900

116,713

passmark_physics

3,667

16,647

passmark_random_string_sorting

129,479

241,849

passmark_single_thread

2,441

3,750

passmark_singlethread

2,441

3,750

DETAILED SPECIFICATIONS

SPECIFICATION

EPYC 8534P

EPYC 9455P

Core Specs

Cores

64

48 -25.0%

Threads

128

96 -25.0%

Base Clock (GHz)

2.3

3.15 +37.0%

Boost Clock (GHz)

3.1

4.4 +41.9%

Frequency (GHz)

2.3

3.15 +37.0%

Turbo Clock (GHz)

3.1

4.4 +41.9%

Multiplier

23

31.5 +37.0%

SMP CPUs

1

1 0.0%

Cache

L1 Cache

64 KB (per core)

80 KB (per core)

L2 Cache

1 MB (per core)

1 MB (per core)

L3 Cache

128 MB (shared)

256 MB (shared)

Power

TDP (W)

200

300 +50.0%

Configurable TDP

155-225 W

240-300 W

Architecture

Architecture

Zen 4c

Zen 5

Codename

Siena

Turin

Generation

EPYC (Zen 4c (Siena))

EPYC (Zen 5 (Turin))

Process Size

5 nm

4 nm

Transistors

35,500 million

66,520 million

Die Size

4x 73 mm²

8x 70.6 mm²

Foundry

TSMC

TSMC

Memory

Memory Support

DDR5

DDR5

Memory Bus

Six-channel

Twelve-channel

Memory Bandwidth

230.4 GB/s

576.0 GB/s

ECC Memory

Yes

Yes

Platform

Socket

AMD Socket SP6

AMD Socket SP5

PCIe

Gen 5, 96 Lanes(CPU only)

Gen 5, 128 Lanes(CPU only)

AMD Multi-Die

IO Process Size

6 nm

6 nm

Interconnect

CXL

—

Gen 2.0

Other

Market

Server/Workstation

Server/Workstation

Production Status

Active

Active

Launch Price

$4950

$4819

Part Number

100-000000875

100-000001563

Package

FC-LGA4844

FC-LGA6096

Bundled Cooler

None

—

View EPYC 8534P Details View EPYC 9455P Details