CPU Comparison

A

AMD

AMD

AMD EPYC 9355P

CORE STATE Turin

CORE SPECS 32 Cores / 64 Threads

CLOCK SPEED 3.55 Base / 4.4 GHz Turbo

CACHE 256 MB (shared)

MAX TDP 280W

ARCHITECTURE Zen 5

nm

PROCESS 4 nm

LAUNCH DATE 2024

VS

A

AMD

AMD

EPYC Embedded 8224P

CORE STATE Siena

CORE SPECS 24 Cores / 48 Threads

CLOCK SPEED 2.55 Base / 3 GHz Turbo

CACHE 64 MB (shared)

MAX TDP 160W

ARCHITECTURE Zen 4c

nm

PROCESS 5 nm

LAUNCH DATE 2023

PERFORMANCE BENCHMARKS

cinebench_cinebench_r15_multicore

8,332

4,187

cinebench_cinebench_r15_singlecore

1,176

590

cinebench_cinebench_r20_multicore

34,719

17,447

cinebench_cinebench_r20_singlecore

4,901

2,462

cinebench_cinebench_r23_multicore

82,666

41,542

cinebench_cinebench_r23_singlecore

11,670

5,864

passmark_data_compression

1,431,968

681,754

passmark_data_encryption

81,945

43,619

passmark_extended_instructions

106,821

46,091

passmark_find_prime_numbers

1,041

286

passmark_floating_point_math

255,177

120,066

passmark_integer_math

414,347

193,256

passmark_multithread

97,255

48,873

passmark_physics

14,521

4,110

passmark_random_string_sorting

180,482

85,505

passmark_single_thread

3,741

2,357

passmark_singlethread

3,741

2,357

DETAILED SPECIFICATIONS

SPECIFICATION

EPYC 9355P

EPYC Embedded 8224P

Core Specs

Cores

32

24 -25.0%

Threads

64

48 -25.0%

Base Clock (GHz)

3.55

2.55 -28.2%

Boost Clock (GHz)

4.4

3 -31.8%

Frequency (GHz)

3.55

2.55 -28.2%

Turbo Clock (GHz)

4.4

3 -31.8%

Multiplier

35.5

25.5 -28.2%

SMP CPUs

1

1 0.0%

Cache

L1 Cache

80 KB (per core)

64 KB (per core)

L2 Cache

1 MB (per core)

1 MB (per core)

L3 Cache

256 MB (shared)

64 MB (shared)

Power

TDP (W)

280

160 -42.9%

Configurable TDP

240-300 W

155-225 W

Architecture

Architecture

Zen 5

Zen 4c

Codename

Turin

Siena

Generation

EPYC (Zen 5 (Turin))

EPYC (Zen 4c (Siena))

Process Size

4 nm

5 nm

Transistors

66,520 million

17,750 million

Die Size

8x 70.6 mm²

2x 73 mm²

Foundry

TSMC

TSMC

Memory

Memory Support

DDR5

DDR5

Memory Bus

Twelve-channel

Six-channel

Memory Bandwidth

576.0 GB/s

230.4 GB/s

ECC Memory

Yes

Yes

Platform

Socket

AMD Socket SP5

AMD Socket SP6

PCIe

Gen 5, 128 Lanes(CPU only)

Gen 5, 96 Lanes(CPU only)

AMD Multi-Die

IO Process Size

6 nm

6 nm

Interconnect

CXL

Gen 2.0

—

Other

Market

Server/Workstation

Server/Workstation

Production Status

Active

Active

Launch Price

$2998

—

Part Number

100-000001521

100-000001418

Package

FC-LGA6096

FC-LGA4844

Bundled Cooler

—

None

View EPYC 9355P Details View EPYC Embedded 8224P Details