AMD EPYC Embedded 9654

The AMD EPYC Embedded 9654 is a Server/Workstation processor in the EPYC 9004 series, built on the Zen 4 architecture under the Genoa codename. It uses AMD Socket SP5 and is manufactured at TSMC on a 5 nm process, with 78,840 million transistors and a die size notation of 12x 72 mm². The part number is 100-100000921. The CPU provides 96 cores and 192 threads, with a 2.40 GHz base clock and a 3.70 GHz boost clock, plus 384 MB of shared L3 cache. The database entry lists an average benchmark score of 0, an empty benchmarks array, no nearest rivals, and a percentile rank of 50, so the specification set is the available record for analysis.

Who Should Consider It

No measured scores are present in the database entry, so workload guidance must be drawn from the listed specifications rather than from benchmark deltas. The 96 cores and 192 threads make the processor a match for thread-dense server workloads such as large-scale virtualization, where concurrent virtual machines can be distributed across the available threads. The 384 MB shared L3 cache is helpful for workloads with large common data sets, and the Twelve-channel DDR5 bus at 460.8 GB/s provides the memory throughput that many parallel threads can consume. Database and analytical tasks are plausible fits because the memory path is ECC-capable and wide. For creation-oriented workloads, multi-threaded rendering or simulation can take advantage of the core count, though the empty benchmark set means no measured rendering score exists. Office workloads are not the main target: the processor is typed as Server/Workstation, and an office workflow will typically exercise only a small fraction of 192 threads. Gaming is also outside the intended scope, as the integrated graphics field is null and the platform is oriented toward high-throughput computing rather than desktop interactivity.

Single-Thread vs Multi-Thread Behavior

The single-thread versus multi-thread profile is set by a 2.40 GHz base clock and a 3.70 GHz boost clock. Single-threaded work can reach the 3.70 GHz boost ceiling, and the Zen 4 core design provides the instruction processing foundation, but the entry contains no benchmark score to measure this directly. Multi-threaded work has 96 cores and 192 threads to draw upon; under full load, the 2.40 GHz base clock is the reference sustained speed. The cache hierarchy is tailored to both directions: 64 KB of L1 per core and 1 MB of L2 per core give each thread private storage, while the shared 384 MB L3 allows all cores to access a common pool. The 460.8 GB/s Twelve-channel memory bandwidth is a strong counterweight to thread starvation: many concurrent memory references can be serviced without immediately saturating the bus. A workload that needs one fast thread will use only a small slice of the processor, whereas a workload that can be decomposed across 192 threads can use nearly every resource in the package.

How It Compares

The nearestRivals field is empty, so the database does not supply any direct rival names, scores, or deltaPct values for this processor. That means no paragraph can assert a position ahead of or behind a specific competing CPU. The only comparative marker is percentileVsAllCpus, which is 50; that value indicates a midpoint placement in the all-CPUs distribution. However, with an average benchmark score of 0 and no benchmark entries, the percentile reads as an unmeasured placeholder rather than a verified result. The processor’s position within the EPYC 9004 series is identifiable from the series field, but its performance relationship to any other SKU is not defined by this record.

FAQ

Q: What is the architecture and socket?

A: It uses the Zen 4 architecture with the Genoa codename, on AMD Socket SP5.

Q: How many cores and threads does it have?

A: It has 96 cores and 192 threads.

Q: What memory support is listed?

A: DDR5 on a Twelve-channel bus, with 460.8 GB/s bandwidth and ECC memory enabled.

Q: How is the cache laid out?

A: L1 is 64 KB per core, L2 is 1 MB per core, and L3 is 384 MB shared.

Q: What PCIe connectivity is provided?

A: PCIe Gen 5, with 128 lanes from the CPU only.

Q: Does it include integrated graphics?

A: No; the integrated graphics field is null.

Power and Thermals

The TDP is 360 W, which places the EPYC Embedded 9654 in a high-power server class. A platform in this TDP class needs a robust thermal solution: high-capacity heatsinks, strong chassis airflow, and cooling infrastructure designed for that heat load. The 2.40 GHz base clock is the listed sustained frequency reference, while the 3.70 GHz boost clock is the headroom for less heavily loaded cores. The multiplier is not unlocked, so there is no user-accessible overclocking path to change that thermal envelope. The processor is built at TSMC on a 5 nm process with 78,840 million transistors, and the 12x 72 mm² package concentrates that transistor budget in a single socket. No integrated graphics are present, so the 360 W figure applies to the CPU package rather than to display hardware. The production status is Active, with a release date of 2023-03-13, so current deployments require a cooling plan for the full 360 W design power.