AMD EPYC Embedded 9554

The AMD EPYC Embedded 9554 is part of the EPYC 9004 series, a 64-core, 128-thread Zen 4 processor with the Genoa codename, built on TSMC’s 5 nm process with 52,560 million transistors in an 8x 72 mm² die configuration. It uses AMD Socket SP5 and is classified in the server/workstation market segment. The processor runs at a 3.10 GHz base clock and 3.75 GHz boost clock, with a 360 W TDP and a locked multiplier. Its part number is 100-100000912. The data record contains an empty benchmarks array, an empty nearestRivals list, an average benchmark score of 0, and a percentileVsAllCpus value of 50. Consequently, quantitative performance interpretation is limited to the architecture and specification fields.

Benchmark Performance

The FACT PACK does not include a single entry in the benchmarks array. Average benchmark score is 0, so there is no measured score to compare against other CPUs. PercentileVsAllCpus is 50, placing the part at the midpoint of the all-CPU distribution in the database. However, because the score field is 0 and no nearest rivals are listed, the percentile is not backed by a populated benchmark result. No deltaPct values exist, meaning exact percentage differences against competitors cannot be quoted.

What can be analyzed is the throughput-oriented specification set present in the pack: 64 cores and 128 threads form a high-parallelism baseline. The cache hierarchy supplies 64 KB of L1 per core, 1 MB of L2 per core, and 256 MB of shared L3, giving each core private low-latency storage and the whole chip a large shared pool. Twelve-channel DDR5 memory support with ECC enabled and 460.8 GB/s bandwidth provides a wide memory path. PCIe Gen 5 with 128 lanes from the CPU offers high I/O capacity. These specifications are consistent with a server/workstation processor designed to feed many cores with data and attach many devices.

The clock range is 3.10 GHz base to 3.75 GHz boost. Within the 360 W TDP envelope, that clock range is one part of the performance equation; the other parts are core count, cache size, memory bandwidth, and PCIe throughput. The multiplier is locked, so frequency adjustment is not available as a tuning path. The absence of benchmark data means the relative performance position cannot be stated in percentages. A 50th-percentile ranking does appear, but with an empty benchmark set, its actionable meaning is limited. The exact deltas that would normally be used in this section are simply not present in the FACT PACK.

How It Compares

The nearestRivals field is empty. No rival names, scores, or deltaPct values are available for comparison. Therefore, a position against any specific competitor cannot be established from this record. The EPYC Embedded 9554’s own data points provide the only context. It is a 64-core, 128-thread part in the EPYC 9004 series, on Socket SP5, with 256 MB shared L3, twelve-channel DDR5 at 460.8 GB/s, and 128 Gen 5 PCIe lanes. It carries a 50th-percentile ranking among all CPUs in the database. With avgBenchmarkScore at 0 and no nearestRivals entries, that percentile is not attached to a measured score or to any named rival. Since the FACT PACK provides no rival entries, no per-rival paragraphs are possible; the comparison section is constrained to the metadata that exists.

Power and Thermals

TDP is 360 W. This is a high thermal envelope and indicates a cooling solution intended for a server/workstation environment rather than a consumer desktop. The processor uses AMD Socket SP5, which is the platform interface for the EPYC 9004 series. Manufacturing is on TSMC’s 5 nm node, with 52,560 million transistors and an 8x 72 mm² die layout. No cooler specification is included in the FACT PACK, so the exact cooling tier cannot be identified by model. The thermal requirement follows from the 360 W TDP. The release date is 2023-03-13. Market segment is server/workstation. No integrated graphics is listed, so the 360 W TDP is attributable to the processor itself and its platform interfaces, not to an integrated GPU. The power characteristics, combined with the locked multiplier, point to a part designed for fixed-operation servers where consistent power and thermal behavior matter more than overclocking headroom.

FAQ

Q: How many cores and threads does the AMD EPYC Embedded 9554 have?

A: It has 64 cores and 128 threads.

Q: What memory configuration does it support?

A: It supports DDR5 memory with a twelve-channel bus, 460.8 GB/s of memory bandwidth, and ECC memory support.

Q: What PCIe capabilities are listed?

A: It has PCIe Gen 5 with 128 lanes from the CPU, and no integrated graphics is listed.

Q: What is the cache hierarchy?

A: L1 cache is 64 KB per core, L2 cache is 1 MB per core, and L3 cache is 256 MB shared.

Q: Which socket and market segment does it target?

A: It uses AMD Socket SP5 and is classified in the server/workstation market segment.

Q: When was it released and is it still in production?

A: The release date is 2023-03-13 and the production status is Active.

Q: What is the clock specification?

A: Base clock is 3.10 GHz, boost clock is 3.75 GHz, and the multiplier is locked.

Who Should Consider It

Because the benchmarks array is empty and average benchmark score is 0, performance-based recommendations cannot be grounded in measured scores. The recommendations below are grounded in the specification fields. Sixty-four cores and 128 threads make the processor a candidate for server and workstation workloads that parallelize across many threads. The 256 MB shared L3 cache reduces the need to repeatedly fetch data from system memory in workloads with large shared datasets. The 460.8 GB/s twelve-channel DDR5 path with ECC is suitable for memory-sensitive tasks that require both bandwidth and reliability. The 128 Gen 5 PCIe lanes support systems with many NVMe drives, accelerators, or network adapters.

For gaming, the FACT PACK lists no integrated graphics and no benchmark scores, so a gaming-oriented recommendation cannot be derived from this record. For content creation, the 64-core, 128-thread configuration indicates strong potential for parallel rendering, transcoding, and simulation, but no creation benchmark scores are available to confirm relative performance. For office workloads, the high core count, ECC memory, and server/workstation classification are beyond typical office needs, and no office benchmark scores are present in the data. The intended audience is clearly the server/workstation segment, reinforced by the 360 W TDP and AMD Socket SP5 platform. The 3.10 GHz base clock and 3.75 GHz boost clock define the operating range, while the locked multiplier removes overclocking as a customization path. The active production status and 2023-03-13 release date make the part a current candidate for embedded server and workstation designs.